Low-cost receivers for radio frequency (RF) communications frequently make use of CMOS technology. An RF receiver front-end includes a down-conversion mixer, which is a circuit that converts input RF signals directly to baseband frequencies by multiplication with a signal from a local oscillator (LO), as illustrated in FIG. 1a, in which an RF signal 100 centred on the radio frequency f0 is multiplied by a signal 110 from a local oscillator at frequency f0 by a mixer 120. The result is a baseband signal 130.
However, because of the fundamental nonlinear characteristics of MOS transistors in the RF frequency range, CMOS mixers do not act as ideal multiplier circuits. Rather, such mixers implement a two-variable polynomial on the input signals:vout=a1v1v2+a21v12v2+a12v1v22+a31v13v2+a13v1v23+a22v12v22+ . . .   (1)
The result of such nonlinearity can be unwanted baseband components, as illustrated in FIG. 1b. An RF signal 140 containing information centred on the radio frequency f0, with two closely spaced interfering signals at higher frequencies f1 and f2, is mixed by the mixer 150 with the local oscillator signal 160. The output signal 170 comprises the desired baseband component and two components at f1-f0 and f2-f0, well outside the baseband, all produced by the first order (a1) term in equation (1), and a weaker tone at f2-f1 within the baseband, produced by the second-order “intermodulation” (IM2) terms (a12 and a21) in equation (1). Other interfering tones are produced by the third-order intermodulation (IM3) terms (a31, a13, and a22) in equation (1). The amount of intermodulation distortion is characterised by the second- and third-order intercept points IIP2 and IIP3 respectively. The higher these values, the lower is the corresponding intermodulation term.
Double-balanced mixer circuits such as the Gilbert cell 200 shown in FIG. 2 have high gain and good suppression of common-mode noise and even-order intermodulation terms, which are also common-mode. The RF input transistors M1 and M2 are known as the transconductors or gm-stage transistors 220, M0 as the bias transistor because of its DC gate voltage setting the DC bias current I0, and the transistors M3, M4, M5, and M6 as the “switching quad” 210. The IIP2 of the Gilbert cell 200 is set by the second-order nonlinearity of the transconductors 220 and the mismatches between the transistors in the switching quad 210 and between the load resistors R1 and R2.
Conventional approaches to IM2 suppression in double-balanced mixers have been found to lack stability over a wide bandwidth, worsen IM3 performance or noise figure, or consume too much power or integrated circuit area.